Thus this XOR configuration seems to be suitable only for CMOS or TTL inputs at A and B and capable of driving only CMOS at output Y. But the problem is the 10K ohm resistor cannot provide the required sink current 0.4mA when the output Y is at Logic ZERO. The Logic LOW voltage is approximately 0V but the sink current limited by the collector resistance 10K ohm.Īs the Logic HIGH input current for TTL is approximately 0.4mA, which is the transistors emitter current and would generate a voltage drop of approximately 4V across 10K ohm resistor. Thus an approximate Logic HIGH voltage V H−0.6V−V CE is available at output terminal Y. Logic gates can be built either with NMOS only or with PMOS only, but then they need an additional resistor and consume energy unnecessarily. A PMOS transistor is switched on by a 0 at the input. A NMOS transistor is switched on by a 1 at the input. When the voltages at terminals A and B are at opposite logic states forward biases the Emitter-Base junction and turns ON the transistor. A NAND gate can be built from MOSFET transistors, of which there are two types: NMOS and PMOS. Second figure shows the circuit diagram of XOR gate, it uses PNP transistor. It should be more concerned and should be limited to 1mA sink of the CMOS. A 0.4mA Logic HIGH current is sufficient for base current but a low at either A or B makes the Emitter current. The CMOS 4000 family is able to source and sink 1mA. Low Speed TTL is able to source 0.4mA and sink 8mA. The collector resistance 6.8K ohm is selected on the basis that to drive the A and B inputs with standard TTL (Transistor Transistor Logic) or CMOS and can be changed according to our application. When the both inputs A and B are at the same Logic Levels, the Emitter to Base junction of the transistor cannot be forward biased, thus the transistor is in OFF state and the output Y is at supply voltage. This turns ON the transistor and the Logic LOW voltage available at the collector of the transistor is approximately equal to 0.6+V L+V CE, where V L is the Logic LOW input and V CE is the Collector to Emitter voltage of the transistor.
When the voltage at A and B terminals are at opposite logic state, a voltage of higher voltage minus lower voltage minus 1.2V (voltage drop between two diodes) forward bias the Emitter-Base junction of the Transistor. First figure shows the Circuit Diagram of XNOR gate, it uses NPN transistor.
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